- ZAM stacks nine functional memory layers vertically inside every compact module
- Each ZAM memory layer reportedly contains exactly 1.125GB of DRAM capacity
- Estimated ZAM bandwidth figures now approach Nvidia HBM4 performance territory closely
Computer memory architecture is set to undergo a significant structural transformation in the coming years.
A new design called Zero-Angle Memory (ZAM) stacks chips vertically rather than spreading them across a flat surface, a shift that could increase data transfer speeds while lowering power consumption.
Intel has thrown its weight behind this technology as a potential replacement for existing HBM memory.
Inside the nine-layer ZAM memory design
Technical diagrams from an upcoming VLSI conference paper have now revealed the internal details of this memory design.
Eight separate DRAM storage layers sit beneath a single control layer within each ZAM module built by the consortium.
That arrangement gives every module a total of nine functional layers stacked on top of one another vertically.
The images from the conference paper show how each of the eight DRAM layers contains exactly 1.125GB of storage capacity.
The basic math, therefore, delivers roughly 9GB of total memory per ZAM module before any overhead deductions.
Three Through-Silicon Vias (TSV) run through the entire vertical stack to connect every layer electrically from top to bottom.
Intel developed the fusion bonding method which creates these TSV connections with extreme precision and reliability.
Every DRAM layer is separated from its neighbour by a silicon substrate only 3 microns thick.
Those TSVs attach to either two or three metal rings on each layer for stable electrical flow.
Bandwidth estimates derived from earlier claims now place ZAM close to HBM4 performance figures from Nvidia‘s Vera Rubin platform.
ZAM targets HBM4-class bandwidth
A Japanese company called Saimemory Corporation leads the commercialization effort for this Intel-backed technology.
Saimemory operates as a wholly owned subsidiary of SoftBank and has not yet released official data rates for this new memory design.
Earlier statements from the company suggested a two to three times speedup over current HBM3 memory standards.
HBM3 currently delivers 819 GBps (or 6.4 Gbps) of bandwidth in its standard configuration today – so a threefold increase from that baseline would give ZAM roughly 2.5 TBps of total throughput for AI processors.
Nvidia’s Vera Rubin AI platform reportedly relies on HBM4 for its highest bandwidth configurations available.
This performance parity puts Intel’s HBM-killer memory tech in direct competition with Nvidia’s preferred memory standard.
At the moment, no working prototype of ZAM has yet been shown to independent reviewers or third-party testing laboratories anywhere in the world.
Manufacturing eight bonded layers without introducing defects remains an unproven and difficult industrial challenge for this consortium.
HBM4 already benefits from Nvidia’s established production roadmap and existing global supply chains across multiple vendors.
A memory standard with superior technical specifications often fails without broad ecosystem adoption and industry backing over time.
The June VLSI conference presentation will determine whether Intel’s HBM-killer claims move beyond paper diagrams into physical reality.
Via HPC WIRE
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